Sarah, Shuo FENG

This paper presents a power-efficient optical modulator driver circuit designed in 130-nm SiGe BiCMOS technology. The proposed driver circuit, based on the breakdown voltage (BV) doubler topology, achieves a significant reduction in power consumption and chip area by merging the data-path emitter-follower (EF) stage and the bias common-emitter (CE) stage into one single stage. The effectiveness of the proposed driver is confirmed by theoretical analysis and simulations. Compared with conventional BV doubler-based topology, the proposed driver improves the power consumption by 21% from 1.11W to 0.92W, with a 3-dB bandwidth of 49.0 GHz and an output voltage swing of 4 Vppd. Simulation results also demonstrate that the proposed driver is capable of supporting PAM-4 optical communications at a data rate of 128 Gb/s, with an output PAM-4 eye width of 0.61 UI and a ratio of level mismatch (RLM) of 95%.

This paper presents a high-speed, large-output swing driver with 2-tap feedforward equalizer (FFE) for optical modulators in 130-nm SiGe BiCMOS process. A breakdown voltage (BV) doubler topology with all-pass filter (APF)-based dynamic bias is applied in the driver to improve the output swing and the bandwidth. A 2-tap fractional-spaced FFE is implemented to compensate for the insufficient bandwidth of optical modulators. Simulation results indicate that the driver achieves an output swing of 4 Vppd and a 3-dB bandwidth of 62.4 GHz with a power consumption of 1.15 W. The performance of the driver is further evaluated in an electrical/optical (E/O) system where a Verilog-A model for Mach-Zehnder Modulator (MZM) with a 3-dB bandwidth of 35 GHz is used. Taking advantages of the 2-tap FFE, the E/O system achieves a 3-dB bandwidth of 50.4 GHz and can support 160-Gb/s PAM-4 optical communications.

Professor Quan Pan's team from the National Exemplary School of Microelectronics of the College of Engineering at the Southern University of Science and Technology (SUSTech) has recently made significant progress in the field of high-performance communication chip design, with research results including a 112-Gb/s Single-Ended PAM-4 Transceiver, a PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver, a 4-Vppd 160-Gb/s PAM-4 Optical Modulator Driver and so on. They conducted a pioneering study on the IEEE P802.3df standard and proposed two feasible exploration options, providing a potential approach for the next-generation wireline communication interface standard. Their research results have been presented in at IEEE European Solid State Circuits Conference (ESSCIRC) 2022, a top conference in integrated circuit design, IEEE International Conference on Integrated Circuits Technology and Applications (ICTA), and IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Professor Quan Pan's team from the National Exemplary School of Microelectronics of the College of Engineering at the Southern University of Science and Technology (SUSTech) has made significant progress in the field of high-performance communication chip design, with research results including a low-power ultra-wideband communication chip for 5G communication, a low-power injection-locked clock signal recovery circuit chip for high-speed wired communication and a high-speed optical communication chip. The research results have been published in the IEEE Journal of Solid-State Circuits (JSSC), a top journal of the IEEE Solid-State Circuits Society, the IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), a top journal of the IEEE Circuit and System Society, and the cover article of the first issue of the high-level national journal, Journal of Semiconductors (JOS). JSSC and TCAS-I are the top academic journals representing the highest international academic standards in the chip field.

The invention discloses a large-output swing amplitude driving circuit, wherein a swing amplitude amplifying module is used for acquiring differential input signals, acquiring a plurality of paths of differential signals according to the differential input signals, outputting one path of differential signals to a main common emitter differential pair, amplifying the swing amplitudes of the rest paths of differential signals to obtain bias voltage signals, and outputting the bias voltage signals to a common base electrode differential module so as to drive the base electrodes of the main common base electrode differential pairs; the main common emitter differential pair is used for enabling the common base differential module to output a differential driving signal according to the differential signal; the tail current source module is used for providing constant tail current for the main common emitter differential pair; the common base electrode differential module comprises n main common base electrode differential pairs which are mutually stacked and connected, and the common base electrode differential module is used for amplifying the swing amplitude of the differential driving signal according to the differential signal after the swing amplitude amplification, so that the output swing amplitude of the driving circuit is increased.

The utility model discloses a kind of cutting pliers, the jaw arm being oppositely arranged including two, two jaw arms side close to each other offers loose slot on one side, installation through-hole is offered on the side inner wall that two loose slots are located remotely from each other, and the internal activity of two installation through-holes installs a useful screw rod, the outside screw of screw rod is set with nut, and nut is in contact with one of jaw arm, the two sides of nut are equipped with third tong arm hole and the 4th tong arm hole, and be located at nut the same side third tong arm hole and the 4th tong arm hole be provided on a jaw arm, jaw arm offers the first tong arm hole far from a lateral roof of screw rod, the lower section in the first tong arm hole is equipped with iron roll, and iron roll is fixed on side of the jaw arm far from screw rod.The utility model can carry out retightening operation to steel wire with labour-saving and subsequent tighten operation by pressing pressing tongs handle.

Dr. Quan Pan, Bachelor's degree in electronic science and technology, University of Science and Technology of China; Doctor's degree in electronic and computer engineering, Hong Kong University of Science and Technology. From 2005 to 2009, he worked as an rf chip engineer in Beijing Times MinXin technology co. LTD. From 2014 to 2018, he worked as a senior executive engineer at eTopus Technology Inc, a silicon valley high-speed hardware startup. Prof. Quan Pan’s main research interests are high-speed analog/RF IC designs, which include Wireline/Wireless high-speed communication ICs (both receiver and transmitter), Serdes/clock and recovery (CDR) circuits, LNA/frequency synthesizer, GaN IC, Si-Photonics. He has published multiple high-quality journals/conference papers, and he has more than 8-year industry experience, including 4-year state-of-the-art industry experience in Silicon Valley IC startup. In 2014, he won the innovation award of the 4th HKUST million dollar entrepreneurship competition, and in 2017, he was awarded the outstanding young author award by IEEE circuit systems association. In 2019, he obtained the Pearl River talent plan project to introduce high-level talents-young top talent. In 2020, he won the excellent academy tutor award of SUSTech. In 2021, he won the excellent teaching award of SUSTech.

Optical communication integrated circuit
Wireline/Serdes/TIA/CDR circuit
Analog/rf integrated circuit
5G/ MMW integrated circuit design
Chip level and board level EMI and noise analysis
high-performance layout optimization analysis
Research on silicon optical interconnection

Chenchang Zhan is an Associate Professor with the School of Microelectronics (National Exemplary School of Microelectronics), the Southern University of Science and Technology (SUSTech), Shenzhen, China. He received the B.Sc. degree in electrical engineering and the M.Sc. degree in microelectronics from Fudan University, Shanghai, China, in 2004 and 2007, respectively, and the Ph.D. degree in electronic and computer engineering from the Hong Kong University of Science and Technology (HKUST), Hong Kong SAR, China, in 2011. From 2006 to 2007, he was an Intern Analog Design Engineer with VeriSilicon, Shanghai, China. From 2011 to 2012, he worked as a post-doctoral Research Associate with HKUST. From 2012 to 2014, he was with Qualcomm Inc., San Diego, CA, as a Senior Engineer, focusing on the design of high-performance power converters for future generations of mobile devices. He then joined SUSTech as an Assistant Professor in Aug. 2014, and was promoted to an Associate Professor in Dec. 2019. His research interests include the analysis and design of analog, mixed-signal and power management integrated circuits and systems for a variety of applications. Up to date, he published 1 book, >70 SCI/EI papers, and was granted with 8 China and 5 US patents. He received the Best Paper Award from IEEE ISIC'2009, Singapore and IEEE EDSSC'2018, Shenzhen, the Best Student Paper Award from IEEE EDSSC'2010, Hong Kong, the Best Student Paper Award from IEEE ISCAS'2011, Rio de Janeiro, Brazil, the 2018 SUSTech Young Faculty Research Award, the 2019 SUSTech Excellent Teacher of the Year Award, the 2019 SUSTech Excellent Residential College Mentor of the Year Award, and the 2020 SUSTech 5-Year Service Award. He served as a Review Committee Member for IEEE APCCAS'2014, a Technical Program Committee member for IEEE ICTA'2018, ICTA’2019 and ICTA’2020, a Guest Editor for Hindawi APEC, a Session Chair/Co-Chair for IEEE ISCAS'2018, ISCAS'2019 and ICTA'2018, as well as a reviewer for many reputational international journals and conferences. He is a Senior Member of IEEE.

Power management and energy harvesting integrated circuits and systems
Analog and mixed-signal integrated circuits
Low-power integrated circuit design methodology

In order to improve the speed and the extinction ratio (ER) of optical signals generated by optical modulators, a driver with high bandwidth and large output voltage swing is essential. Limited by small collector-emitter breakdown voltage (BVCEO) of SiGe hetero-junction bipolar transistor (HBT), a traditional cascode-based driver with the base of each cascode transistor biased at a fixed voltage can only achieve an output voltage swing smaller than BVCEO. To relieve the issue, a BV doubler topology is adopted in the output stage of the proposed diver core. Since the emitter voltage VE, the base voltage VB and the collector voltage VC of cascode transistors are in phase, and VE varies with VB, the output voltage swing of the output stage can be twice that of the conventional cascode-based driver by properly controlling the swing and the phase of VB.

This project do research on inductive-peaking-based bandwidth extension techniques and apply them in the high-swing driver stage circuit in 130-nm SiGe BiCMOS process. We have demonstrated the effectiveness of T-coils and three-ends transformers in an electrical/optical (E/O) system where a Verilog-A model for Mach-Zehnder Modulator (MZM) with a 3-dB bandwidth of 35 GHz is used. I will continuing to do research on the distributed output networks in transmitters (TX).

Coming soon.

We designed a high precision, low power consumption, fast response relaxation oscillator with integrated low-dropout regulator (LDO), voltage and current reference (VCR) and oscillator (OSC) modules. Among them, the oscillator module compensates the frequency deviation with high accuracy by adding digital control and using 1.5 times the reference current to achieve high frequency stability. The design is simulated in TSMC 180-nm process, and the layout and verification are completed. The overall performance extremely well meets all the conventional and additional specifications of the topic and has outstanding performance in frequency temperature stability, voltage stability, start-up time, static power consumption, which has the potential for tapeout.